Senior Design Engineer sought by ARM Inc. in Austin, TX to develop SystemVerilog testbenches using UVM for block-level functional verification of the coherent interconnect. Min Req: Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or related field and 3 years' experience or, in the alternative, a Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or related field and 5 years' experience. Experience in microprocessor or SoC validation, including developing object-oriented transaction-based testbenches; multiprocessing microarchitecture including cache coherence, bus and high-speed interface protocols, etc; specification and creation of SystemVerilog testbenches in UVM/OVM; verilog language and associated software simulators; object-oriented programming, data structures, and algorithms; functional coverage driven verification methods. Send resume to: firstname.lastname@example.org. Reference #2015.