Design Engineer (Chandler, AZ) sought by ARM Inc. Responsible for implementation techniques that result in best power efficiency, highest performance, and lowest cost for ARM processor cores. Min Req: Master's degree in Electrical Engineering, Computer Engineering, or related field. At least 1 yr. exp. in: Physical implementation in advanced technologies; Low latency clock tree synthesis/optimization, area/power efficient floorplanning and static timing analysis; Industry standard EDA toolsets from Cadence (including Innovus, Genus, Tempus) & Synopsys (including IC Compiler, PrimeTime, Design Compiler); Programming skills in TCL, Unix or Linux shell scripting; Top and/or block level physical implementation tradeoffs such as power grid, floorplans and area in state-of-art submicron CMOS designs. Send resume to: firstname.lastname@example.org. Reference #35867.